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octal, 12-/16-bit dac, i 2 c ? , 5ppm/c on- chip reference in 4mm x 4mm lfcsp preliminary technical data ad5629r/ad5669r rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. features low power, smallest-pin-compatible octal dacs ad5669r: 16 bits ad5629r: 12 bits 4mm x 4mm 16-lead lfcsp and 16-lead tssop user selectable on-chip 1.25 v/2.5 v, 5 ppm/c reference power down to 400 na @ 5 v, 200 na @ 3 v 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to zero scale or midscale 3 power-down functions hardware ldac and clr functions i 2 c-compatible serial interface supports standard (100 khz) and fast (400 khz) modes applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources general description the ad5629r/ad5669r devices are low power, octal, 12-/16- bit, buffered voltage-output dacs. all devices operate from a single 2.7 v to 5.5 v supply and are guaranteed monotonic by design. the ad5629r/ad5669r has an on-chip reference with an internal gain of 2. the ad5629r/ad5669r has a user selectable 1.25 v 5 ppm/c reference, giving a full-scale output range of 2.5 v or a 2.5 v 5 ppm/c reference, giving a full-scale output range of 5 v depending on the option selected. the on-chip reference is off at power-up, allowing the use of an external refer- ence. the internal reference is enabled via a software write. the ad5669/ad5629 require an external reference voltage to set the output range of the dac. the part incorporates a power-on reset circuit that ensures that the dac output powers up to 0 v (ad5629r/ad5669r) or midscale (ad5669r-3) and remains powered up at this level until a valid write takes place. the part contains a power-down feature that reduces the current consumption of the device to 400 na at 5 v and provides software-selectable output loads while in power- down mode for any or all dac channels. functional block diagram interface logic input register sda ldac gnd v out h v dd ldac v refin / v refout scl a d 5 6 2 9r/ad5669r clr 1.25v/2.5v ref v out a v out b v out c v out d v out e v out f v out g dac register string dac a buffer input register dac register string dac b buffer input register dac register string dac c buffer input register dac register string dac d buffer input register dac register string dac e buffer input register dac register string dac f buffer input register dac register string dac g buffer input register dac register string dac h buffer power-down logic power-on reset a0 figure 1 product highlights 1. octal, 12-/16-bit dac. 2. on-chip 1.25 v/2.5 v, 5 ppm/c reference. 3. available in 16-lead lfcsp/16-lead tssop. 4. power-on reset to 0 v or midscale. 5. power-down capability. when powered down, the dac typically consumes 200 na at 3 v and 400 na at 5 v.
ad5629r/ad5669r preliminary technical data rev. pra | page 2 of 33 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ac characteristics ........................................................................ 7 ? i2c timing characteristics ......................................................... 8 ? absolute maximum ratings .......................................................... 10 ? esd caution ................................................................................ 10 ? pin configurations and function descriptions ......................... 11 ? typical performance characteristics ........................................... 12 ? terminology .................................................................................... 21 ? theory of operation ...................................................................... 23 ? d/a section ................................................................................. 23 ? resistor string ............................................................................. 23 ? internal reference ...................................................................... 23 ? output amplifier ........................................................................ 24 ? serial interface ............................................................................ 24 ? write operation.......................................................................... 24 ? read operation........................................................................... 24 ? input shift register .................................................................... 27 ? internal reference register ....................................................... 27 ? power-on reset .......................................................................... 27 ? power-down modes .................................................................. 27 ? clear code register ................................................................... 28 ? ldac function .......................................................................... 30 ? power supply bypassing and grounding ................................ 30 ? outline dimensions ....................................................................... 32 ? ad5629r ordering guide ........................................................ 33 ? ad5669r ordering guide ........................................................ 33 ? revision history
ad5629r/ad5669r preliminary technical data rev. pra | page 3 of 33 specifications v dd = 4.5 v to 5.5 v, r l = 2 k? to gnd, c l = 200 pf to gnd, v refin = v dd . all specifications t min to t max , unless otherwise noted. table 1. a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments static performance 2 ad5629r resolution 12 12 bits relative accuracy 0.5 2 0.5 1 lsb see figure 5 differential nonlinearity 0.25 0.25 lsb guaranteed monotonic by design (see figure 7) ad5669r resolution 16 16 bits relative accuracy 8 32 8 16 lsb see figure 4 differential nonlinearity 1 1 lsb guaranteed monotonic by design (see figure 6) zero-code error 1 9 1 9 mv all 0s loaded to dac register (see figure 19) zero-code error drift 2 2 v/c full-scale error ?0.2 ?1 ?0.2 ?1 % fsr all 1s loaded to dac register (see figure 21) gain error 1 1 % fsr gain temperature coefficient 2.5 2.5 ppm of fsr/c offset error 1 9 1 9 mv dc power supply rejection ratio C80 C80 db v dd 10% dc crosstalk (external reference) 10 10 v due to full-scale output change, r l = 2 k? to gnd or v dd 5 5 v/ma due to load current change 10 10 v due to powering down (per channel) dc crosstalk (internal reference) 25 25 v due to full-scale output change, r l = 2 k? to gnd or v dd 10 10 v/ma due to load current change output characteristics 3 output voltage range 0 v dd 0 v dd v capacitive load stability 2 2 nf r l = 10 10 nf r l = 2 k? dc output impedance 0.5 0.5 ? short-circuit current 30 30 ma v dd = 5 v power-up time 4 4 s coming out of power-down mode, v dd = 5 v reference inputs reference current 40 50 40 50 a v ref = v dd = 5.5 v (per dac channel) reference input range 0 v dd 0 v dd v reference input impedance 14.6 14.6 k? reference output(1.25v) output voltage 1.247 1.253 1.247 1.253 a at ambient reference input range 5 5 10 ppm/ ? c output impedance 7.5 7.5 k? reference output(2.5v) output voltage 2.495 2.505 2.495 2.505 a at ambient reference input range 5 5 10 ppm/ ? c output impedance 7.5 7.5 k? logic inputs 3 input current 3 3 a all digital inputs
ad5629r/ad5669r preliminary technical data rev. pra | page 4 of 33 a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments input low voltage, v inl 0.8 0.8 v v dd = 5 v input high voltage, v inh 2 2 v v dd = 5 v pin capacitance 3 3 pf power requirements v dd 4.5 5.5 4.5 5.5 v all digital inputs at 0 or v dd , dac active, excludes load current i dd (normal mode) 4 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 1.3 1.8 1.3 1.8 ma internal reference off v dd = 4.5 v to 5.5 v 2 2.5 2 2.5 ma internal reference on i dd (all power-down modes) 5 v dd = 4.5 v to 5.5 v 0.4 1 0.4 1 a v ih = v dd and v il = gnd 1 temperature range is ?40c to +105c, typi cal at 25c. 2 linearity calculated using a reduced code range of ad5629r (code 32 to code 4064) and ad 5669r (code 512 to 65,024). output unl oaded. 3 guaranteed by design and characterization; not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all eight dacs powered down.
ad5629r/ad5669r preliminary technical data rev. pra | page 5 of 33 v dd = 2.7 v to 3.6 v, r l = 2 k? to gnd, c l = 200 pf to gnd, v refin = v dd . all specifications t min to t max , unless otherwise noted. table 2. a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments static performance 2 ad5629r resolution 12 12 bits relative accuracy 0.5 2 0.5 1 lsb see figure 5 differential nonlinearity 0.25 0.25 lsb guaranteed monotonic by design (see figure 7) ad5669r resolution 16 16 bits relative accuracy 8 32 8 16 lsb see figure 4 differential nonlinearity 1 1 lsb guaranteed monotonic by design (see figure 6) zero-code error 1 9 1 9 mv all 0s lo aded to dac register (see figure 19) zero-code error drift 2 2 v/c full-scale error ?0.2 ?1 ?0.2 ?1 % fsr all 1s loaded to dac register (see figure 21) gain error 1 1 % fsr gain temperature coefficient 2.5 2.5 ppm of fsr/c offset error 1 9 1 9 mv dc power supply rejection ratio C80 C80 db v dd 10% dc crosstalk (external reference) 10 10 v due to full-scale output change, r l = 2 k? to gnd or v dd 5 5 v/ma due to load current change 10 10 v due to powering down (per channel) dc crosstalk (internal reference) 25 25 v due to full-scale output change, r l = 2 k? to gnd or v dd 10 10 v/ma due to load current change output characteristics 3 output voltage range 0 v dd 0 v dd v capacitive load stability 2 2 nf r l = 10 10 nf r l = 2 k? dc output impedance 0.5 0.5 ? short-circuit current 30 30 ma v dd = 3 v power-up time 4 4 s coming out of power-down mode, v dd = 3 v reference inputs reference current 40 50 40 50 a v ref = v dd = 3.6 v (per dac channel) reference input range 0 v dd 0 v dd reference input impedance 14.6 14.6 k? reference output output voltage ad5629r/ad5669r 1.247 1.253 1.247 1.253 v at ambient reference tc 3 5 5 15 ppm/c reference output impedance 7.5 7.5 k? logic inputs 3 input current 3 3 a all digital inputs input low voltage, v inl 0.8 0.8 v v dd = 3 v input high voltage, v inh 2 2 v v dd = 3 v pin capacitance 3 3 pf power requirements v dd 2.7 3.6 2.7 3.6 v all digital inputs at 0 or v dd ,
ad5629r/ad5669r preliminary technical data rev. pra | page 6 of 33 a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments dac active, excludes load current i dd (normal mode) 4 v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 1.2 1.5 1.2 1.5 ma internal reference off v dd = 2.7 v to 3.6 v 1.7 2.25 1.7 2.25 ma internal reference on i dd (all power-down modes) 5 v dd = 2.7 v to 3.6 v 0.2 1 0.2 1 a v ih = v dd and v il = gnd 1 temperature range is ?40c to +105c, typi cal at 25c. 2 linearity calculated using a re duced code range of ad5629r (code 32 to code 4064) and ad5669r (co de 512 to 65024). output unl oaded. 3 guaranteed by design and characterization; not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all eight dacs powered down.
ad5629r/ad5669r preliminary technical data rev. pra | page 7 of 33 ac characteristics v dd = 2.7 v to 5.5 v, r l = 2 k? to gnd, c l = 200 pf to gnd, v refin = v dd . all specifications t min to t max , unless otherwise noted. table 3. parameter 1, 2 min typ max unit conditions/comments 3 output voltage settling time 6 10 s ? to ? scale settling to 2 lsb slew rate 1.5 v/s digital-to-analog glitch impulse 4 nv-s 1 lsb change around major carry (see figure 49) digital feedthrough 0.1 nv-s reference feedthrough ?90 db v ref = 2 v 0.1 v p-p, frequency = 10 hz to 20 mhz digital crosstalk 0.5 nv-s analog crosstalk 2.5 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 340 khz v ref = 2 v 0.2 v p-p total harmonic distortion ?80 db v ref = 2 v 0.1 v p-p, frequency = 10 khz output noise spectral density 120 nv/hz dac code = 0x8400, 1 khz 100 nv/hz dac code = 0x8400, 10 khz output noise 15 v p-p 0.1 hz to 10 hz 1 guaranteed by design and characterization; not production tested. 2 see the terminology section. 3 temperature range is ?40c to +105c, typi cal at 25c.
ad5629r/ad5669r preliminary technical data rev. pra | page 8 of 33 i2c timing characteristics v dd = 2.7 v to 5.5 v; all specifications t min to t max , f scl = 400 khz, unless otherwise noted. table 4. parameter conditions min max unit description f scl 1 standard mode 100 khz serial clock frequency fast mode 400 khz t 1 standard mode 4 s t high , scl high time fast mode 0.6 s t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns t 4 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s t 5 standard mode 4.7 s t su;sta , setup time for a repeated start condition fast mode 0.6 s t 6 standard mode 4 s t hd;sta , hold time (repeated) start condition fast mode 0.6 s t 7 standard mode 4.7 s t buf , bus-free time between a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for a stop condition fast mode 0.6 s t 9 standard mode 1000 ns t rda , rise time of sda signal fast mode 300 ns t 10 standard mode 300 ns t fda , fall time of sda signal fast mode 300 ns t 11 standard mode 1000 ns t rcl , rise time of scl signal fast mode 300 ns t 11a standard mode 1000 ns t rcl1 , rise time of scl signal after a repeated start condition and after an acknowledge bit fast mode 300 ns t 12 standard mode 300 ns t fcl , fall time of scl signal fast mode 300 ns t 13 standard mode 10 ns ldac pulse width low fast mode 10 ns t 14 standard mode 300 ns falling edge of ninth scl clock pulse of last byte of a valid write to ldac falling edge fast mode 300 ns t 15 standard mode 20 ns clr pulse width low fast mode 20 ns t sp 2 fast mode 0 50 ns pulse width of spike suppressed 1 the sda and scl timing is measured with the input filters enabled. switching off the input filters improves the transfer rate but has a negative effect on emc behavior of the part. 2 input filtering on the scl and sda inputs suppresses noise spikes that are less than 50 ns for fast mode, or less than 10 ns f or high speed mode.
ad5629r/ad5669r preliminary technical data rev. pra | page 9 of 33 scl sda ps s p t 8 t 6 t 5 t 3 t 10 t 9 t 4 t 6 t 1 t 2 t 11 t 12 t 14 clr t 13 t 15 ldac* t 7 *asynchronous ldac update mode. 06341-003 figure2. serial write operation
ad5629r/ad5669r preliminary technical data rev. pra | page 10 of 33 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v v out to gnd ?0.3 v to v dd + 0.3 v v refin /v refout to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max ) +150c tssop package power dissipation (t j max ? t a )/ ja ja thermal impedance 150.4c/w reflow soldering peak temperature snpb 240c pb free 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5629r/ad5669r preliminary technical data rev. pra | page 11 of 33 pin configurations and function descriptions 00000-000 12 11 10 1 3 4 vd vf vh 9 clr ldac v 2 a0 va 6 v e 5 v c 7 v g 8 v 1 6 s c l 1 5 s d a 1 4 g n d 1 3 v b top view ad5669r/29r d d out out out out out out out ref out figure 2. 16-lead lfcsp (cp-16-17) x xxxx-xxx 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 a0 v dd v out a v out g v out e v out c ldac sda gnd v out b v out h v refin /v refout clr v out f v out d scl ad5629r/ ad5669r top view (not to scale) figure 3. 16-lead tssop (ru-16) table 6. pin function descriptions pin no. 16-lead lfcsp 16-lead tssop mnemonic description 15 1 ldac pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows all dac outputs to simultan eously update. alternatively, this pin can be tied permanently low. 16 2 a0 address input. sets the least signif icant bit of the 7-bit slave address. 1 3 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in pa rallel with a 0.1 f capacitor to gnd. 2 4 v out a analog output voltage from dac a. the outp ut amplifier has rail-to-rail operation. 11 13 v out b analog output voltage from dac b. the outp ut amplifier has rail-to-rail operation. 3 5 v out c analog output voltage from dac c. the outp ut amplifier has rail-to-rail operation. 10 12 v out d analog output voltage from dac d. the outp ut amplifier has rail-to-rail operation. 6 8 v refin /v refout the ad5629r/ad5669r has a common pin for reference input and reference output. when using the internal reference, this is the re ference output pin. when using an external reference, this is the reference input pin. the default for this pin is as a reference input. 7 9 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the input register and the dac register are updated with the data contained in the clr code registerzero, midscale, or full scale. default setting clears the output to 0 v. 4 6 v out e analog output voltage from dac e. the outp ut amplifier has rail-to-rail operation. 9 11 v out f analog output voltage from dac f. the o utput amplifier has rail-to-rail operation. 5 7 v out g analog output voltage from dac g. the outp ut amplifier has rail-to-rail operation. 8 10 v out h analog output voltage from dac h. the outp ut amplifier has rail-to-rail operation. 12 14 gnd ground reference point for all circuitry on the part. 13 15 sda serial data input. this device has a 32-bit shift register. data is clocked into the register on the falling edge of the serial clock input. 14 16 scl serial clock input. data is clocke d into the input shift register on the falling edge of the serial clock input.
ad5629r/ad5669r preliminary technical data rev. pra | page 12 of 33 typical performance characteristics figure 4. inl ad5669rexternal reference figure 5. inl ad5629rexternal reference figure 6. dnl ad5669rexternal reference figure 7. dnl ad5629rexternal reference figure 8. inl ad5669r-2/ad5669r-3 figure 9 figure 10. inl ad5629r-2
ad5629r/ad5669r preliminary technical data rev. pra | page 13 of 33 figure 11. dnl ad5669r-2/ad5669r-3 figure 12. dnl ad5629r-2 figure 13. inl ad5669r-1 figure 14. inl ad5629r-1 figure 15. dnl ad5629r-1
ad5629r/ad5669r preliminary technical data rev. pra | page 14 of 33 figure 16. figure 17. gain error and full-scale error vs. temperature figure 18. figure 19. zero-scale error and offset error vs. temperature figure 20. figure 21. gain error and full-scale error vs. supply voltage figure 22. figure 23. zero-scale error and offset error vs. supply voltage
ad5629r/ad5669r preliminary technical data rev. pra | page 15 of 33 figure 24. figure 25. i dd histogram with external reference figure 26. i dd histogram with in ternal reference figure 27. figure 28. headroom at rails vs. source and sink figure 29. figure 30. ad5669r-2/ad5669r-3 source and sink capability
ad5629r/ad5669r preliminary technical data rev. pra | page 16 of 33 figure 31. figure 32. ad5669r-1 source and sink capability figure 33. figure 34. supply current vs. code figure 35. figure 36. supply current vs. temperature figure 37. figure 38. supply current vs. supply voltage
ad5629r/ad5669r preliminary technical data rev. pra | page 17 of 33 figure 39. figure 40. supply current vs. logic input voltage figure 41. figure 42. full-scale settling time, 5 v figure 43. power-on reset to 0 v figure 44. figure 45. power-on reset to midscale
ad5629r/ad5669r preliminary technical data rev. pra | page 18 of 33 figure 46. figure 47. exiting power-down to midscale figure 48. figure 49. digital-to-analog glitch impulse (negative) figure 50. figure 51. analog crosstalk figure 52. figure 53. dac-to-dac crosstalk
ad5629r/ad5669r preliminary technical data rev. pra | page 19 of 33 figure 54. figure 55. 0.1 hz to 10 hz output noise plot, external reference figure 56 figure 57. 0.1 hz to 10 hz output noise plot, internal reference figure 58. figure 59. 0.1 hz to 10 hz output noise plot, internal reference figure 60. figure 61. noise spectral density, internal reference
ad5629r/ad5669r preliminary technical data rev. pra | page 20 of 33 figure 62. figure 63. total harmonic distortion figure 64. figure 65. settling time vs. capacitive load figure 66. figure 67. hardware clr figure 68. figure 69. multiplying bandwidth
ad5629r/ad5669r preliminary technical data rev. pra | page 21 of 33 terminology relative accuracy for the dac, relative accuracy, or integral nonlinearity (inl), is a measure of the maximum deviation in lsbs from a straight line passing through the endpoints of the dac transfer function. figure 4 to figure 5, figure 8 to figure 10, and figure 13 to figure 14 show plots of typical inl vs. code. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed mono- tonic by design. figure 6 to figure 7, figure 11 to figure 12, and error! reference source not found. to error! reference source not found. show plots of typical dnl vs. code. offset error offset error is a measure of the difference between the actual v out and the ideal v out , expressed in millivolts in the linear region of the transfer function. offset error is measured on the ad5669r with code 512 loaded into the dac register. it can be negative or positive and is expressed in millivolts. zero-code error zero-code error is a measure of the output error when zero code (0x0000) is loaded into the dac register. ideally, the output should be 0 v. the zero-code error is always positive because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in millivolts. figure 23 shows a plot of typical zero-code error vs. temperature. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percentage of the full-scale range. zero-code error drift zero-code error drift is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. full-scale error full-scale error is a measure of the output error when full-scale code (0xffff) is loaded into the dac register. ideally, the output should be v dd C 1 lsb. full-scale error is expressed as a percentage of the full-scale range. figure 17 shows a plot of typical full-scale error vs. temperature. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 49. dc power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in decibels. v ref is held at 2 v, and v dd is varied 10%. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac (or soft power-down and power-up) while monitoring another dac kept at midscale. it is expressed in microvolts. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in microvolts per milliamp. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (that is, ldac is high). it is expressed in decibels. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device, but is measured when the dac is not being written to. it is specified in nv-s and measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s. analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping ldac high, and then pulsing ldac low and monitoring the output of the dac whose digital code has not changed. the area of the glitch is expressed in nv-s. dac-to-dac crosstalk
ad5629r/ad5669r preliminary technical data rev. pra | page 22 of 33 dac-to-dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s or vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in decibels.
ad5629r/ad5669r preliminary technical data rev. pra | page 23 of 33 theory of operation d/a section the ad5629r/ad5669r are fabricated on a cmos process. the architecture consists of a string of dacs followed by an output buffer amplifier. each part includes an internal 1.25 v/2.5 v, 5 ppm/c reference with an internal gain of 2. figure 71 shows a block diagram of the dac architecture. figure 70 dac architecture for internal reference configuration figure 71. dac architecture for external reference configuration because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n refin out d v v 2 the ideal output voltage when using the internal reference is given by ? ? ? ? ? ? = n refout out d v v 2 2 where: d = decimal equivalent of the binary code that is loaded to the dac register. 0 to 4095 for ad5629r (12 bits). 0 to 65,535 for ad5669r (16 bits). n = the dac resolution. resistor string the resistor string section is shown in figure 72. it is simply a string of resistors, each of value r. the code loaded into the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. 05302-053 to output amplifier r r r r r figure 72. resistor string internal reference the ad5629r/ad5669r have an on-chip reference with an internal gain of 2. the ad5629r/ad5669r have a 1.25 v, 5 ppm/c reference, giving a full-scale output of 2.5 v; or a 2.5 v, 5 ppm/c reference, which will only work from 4.5 to 5.5vgiving a full-scale output of 5 v. the on-board reference is off at power-up, allowing the use of an external reference. the internal reference is enabled via a write to the control register (see table 8). the internal reference associated with each part is available at the v refout pin. a buffer is required if the reference output is used to drive external loads. when using the internal reference, it is recommended that a 100 nf capacitor be placed between the reference output and gnd for reference stability. individual channel power-down is not supported while using the internal reference.
ad5629r/ad5669r preliminary technical data rev. pra | page 24 of 33 output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . the amplifier is capable of driving a load of 2 k? in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 30 and figure 32. the slew rate is 1.5 v/s with a ? to ? scale settling time of 10 s. serial interface the ad5629r/ad5669r have 2-wire i 2 c-compatible serial interfaces (refer to the i 2 c-bus specification , version 2.1, january 2000, available from philips semiconductor). the ad5629r/ad5669r can be connected to an i 2 c bus as a slave device, under the control of a ma ster device. see figure x for a timing diagram of a typical write sequence. the ad5629r/ad5669r support stan dard (100 khz) and fast (400 khz) modes. high speed operation is only available on selected models. see the ordering guide for a full list of models. support is not provided for 10-bit addressing and general call addressing. the ad5629r/ad5669r each has a 7-bit slave address. the part have a slave address whose five msbs are 10101, and the two lsbs are set by the state of the a0 address pin, which determines the state of the a0 and a1 address bits. the facility to make hardwired changes to the a0 pin allows the user to incorporate up to three of these devices on one bus, as outlined in table 7. table 7. addr pin settings (16-lead package) a0 pin connection a1 a0 v dd 0 0 nc gnd 1 0 1 1 the 2-wire serial bus protocol operates as follows: 1. the master initiates data tran sfer by establishing a start condition when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7- bit slave address. the slave address corresponding to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. when all data bits have been read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master brings the sda line low before the 10 th clock pulse, and then high during the 10 th clock pulse to establish a stop condition. write operation when writing to the ad5629r/ad5669r, the user must begin with a start command followed by an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the ad5629r/ad5669r requires two bytes of data for the dac and a command byte that controls various dac functions. three bytes of data must therefore be written to the dac, the command byte followed by the most significant data byte and the least significant data byte, as shown in figures. after these data bytes are acknowledged by the ad5629r/ad5669r, a stop condition follows. read operation when reading data back from the ad5629r/ad5669r, the user begins with a start command followed by an address byte (r/ w = 1), after which the dac acknowledges that it is prepared to transmit data by pulling sda low. two bytes of data are then read from the dac, which are both acknowledged by the master as shown in figure 74 and figure xx. a stop condition follows.
ad5629r/ad5669r preliminary technical data rev. pra | page 25 of 33 frame 2 command byte frame 1 slave address 19 9 1 scl start by master ack. by ad56x9 ack. by ad56x9 sda r/w db23 a0 a1 1 1 0 1 0 db22 db21 db20 db19 db18 db17 db16 19 9 1 ack. by ad56x9 ack. by ad56x9 frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 06341-103 figure 73. i 2 c write operation frame 2 command byte frame 1 slave address 19 9 1 scl start by master ack. by ad56x9 ack. by master sda r/w db23 a0 a1 1 1 0 1 0 db22 db21 db20 db19 db18 db17 db16 19 9 1 ack. by master no ack. frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 06341-101 figure 74. i 2 c read operation
ad5629r/ad5669r preliminary technical data rev. pra | page 26 of 33 table 8. command definitions command c3 c2 c1 c0 description 0 0 0 0 write to input register n 0 0 0 1 update dac register n 0 0 1 0 write to input register n, update all (software ldac ) 0 0 1 1 write to and update dac channel n 0 1 0 0 power down/power up dac 1 0 1 0 1 load clear code register 0 1 1 0 load ldac register 0 1 1 1 reset (power-on reset) 1 0 0 0 set up internal ref register 1 0 0 1 enable multiple byte mode C C C C reserved 1 1 1 1 reserved table 9. address commands address (n) a3 a2 a1 a0 selected dac channel 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 0 1 0 0 dac e 0 1 0 1 dac f 0 1 1 0 dac g 0 1 1 1 dac h 1 1 1 1 all dacs 1 available on ad5629r and ad5669r versions only.
ad5629r/ad5669r preliminary technical data rev. pra | page 27 of 33 input shift register the input shift register is 24 bits wide. data is loaded into the device as a 24-bit word under the control of a serial clock input, scl. the timing diagram for this operation is shown in figure x. the eight msbs make up the command byte. db23-db20 are the command bits (c3, c2, c1, and c0) that control the mode of operation of the device. see table 9 for details. the last four bits of the first byte are th e address bits (a3, a2, a1, and a0). see table 10 for details. the rest of the bits are the 16-/12- bit data word. the data word comprises the 16-/12-bit input code followed by four dont cares for the device (see figure 57 and figure 58). multiple byte operation multiple byte operation is supported on the ad5629r /ad5669r.command 1001 is reserved for multiple byte operation(see table 8) a 2-by te operation is useful for applications that require fast da c updating and do not need to change the command byte. the s bit (db22) in the command register can be set to 1 for 2-byte mode of operation (see figure 62). for standard 3-byte and 4-by te operation, the s bit (db22) in the command byte should be set to 0 (see figure 61). db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command dac address dac data dac data command byte datahighbyte data low byte 06341-108 figure 75. ad5669r/ad5669 input register contents db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x command dac address dac data dac data command byte datahighbyte data low byte 06341-108 figure 76. ad5629r/ad5629 input register contents internal reference register the internal reference is available on all versions. the on-board reference is off at power-up by default. this allows the use of an external reference if the application requires it. the on-board reference can be turned on or off by a user-programmable internal ref register by setting bit db0 high or low (see table 10). db1 selects the internal reference value. when db1 is set to 1 the 1.25v reference is selected. when db1 is set to 0 the 2.5v internal reference is selected. command 1000 is reserved for setting the internal ref register (see table 8). table 12 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device. command 1000 is not functional in ad5669/29 models because there is no internal reference available. power-on reset the ad5629r/ad5669r family contains a power-on reset circuit that controls the output voltage during power-up. the ad5629r/ad5669r dac output powers up to 0 v, and the ad5669r-3 dac output powers up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. there is also a software executable reset function that resets the dac to the power-on reset code. command 0111 is reserved for this reset function (see table 8). any events on ldac or clr during power-on reset are ignored. power-down modes the ad5629r/ad5669r contain four separate modes of operation. command 0100 is reserved for the power-down function (see table 8). these modes are software-programmable by setting two bits, bit db9 and bit db8, in the control register. table 12 shows how the state of the bits corresponds to the mode of operation of the device. any or all dacs (dac h to dac a) can be powered down to the selected mode by setting the corresponding eight bits (db7 to db0) to 1. see table 13. internal reference setup db9 db8 operating mode 0 0 internal reference off
ad5629r/ad5669r preliminary technical data rev. pra | page 28 of 33 0 1 2.5v interenal reference on 1 0 internal reference off 1 1 1.25v internal reference on table 14 for the contents of the input shift register during power- down/power-up operation. when using the internal reference, only all channel power-down to the selected modes is supported. when both bits are set to 0, the part works normally with its normal power consumption of 1.3 ma at 5 v. however, for the three power-down modes, the supply current falls to 0.4 a at 5 v (0.2 a at 3 v). not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode. there are three different options. the output is connected internally to gnd through either a 1 k? or a 100 k? resistor, or it is left open-circuited (three-state). the output stage is illustrated in figure 77. the bias generator of the selected dac(s), output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. the internal reference is powered down only when all channels are powered down. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 4 s for v dd = 5 v and for v dd = 3 v. see figure 47 for a plot. any combination of dacs can be powered up by setting pd1 and pd0 to 0 (normal operation). the output powers up to the value in the input register ( ldac low) or to the value in the dac register before powering down ( ldac high). clear code register the ad5629r/ad5669r have a hardware clr pin that is an asynchronous clear input. the clr input is falling edge sensitive. bringing the clr line low clears the contents of the input register and the dac registers to the data contained in the user-configurable clr register and sets the analog outputs accordingly. this function can be used in system calibration to load zero scale, midscale, or full scal e to all channels together. these clear code values are user-programmable by setting two bits, bit db1 and bit db0, in the clr control register (see table 15). the default setting clears the outputs to 0 v. command 0101 is reserved for loading the clear code register (see table 8). the part exits clear code mode on the 32 nd falling edge of the next write to the part. if clr is activated during a write sequence, the write is aborted. the clr pulse activation timethe falling edge of clr to when the output starts to changeis typically 280 ns. however, if outside the dac linear region, it typically takes 520 ns after executing clr for the output to start changing (see figure 67). see table 16 for contents of the input shift register during the loading clear code register operation.
ad5629r/ad5669r preliminary technical data rev. pra | page 29 of 33 table 10. internal reference register internal ref register (db0) action 0 reference off (default) 1 reference on table 11. 32-bit input shift register contents for reference set-up command lsb db23 db22 db21 db20 db19 db18 db17 db16 db15 to db2 db1 db0 1 0 0 0 x x x x x 1/0 1/0 command bits (c3 to c0) address bits (a3 to a0)dont cares dont cares 2.5v/1.25v internal ref internal ref on/off table 12. power-down modes of operation db9 db8 operating mode 0 0 normal operation power-down modes 0 1 1 k? to gnd 1 0 100 k? to gnd 1 1 three-state table 13. internal reference setup db9 db8 operating mode 0 0 internal reference off 0 1 2.5v interenal reference on 1 0 internal reference off 1 1 1.25v internal reference on table 14. 32-bit input shift register contents for power-down/power-up function lsb db23 db22 db21 db20 db19 db18 db17 db16 db15 to db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 x x x x x pd1 pd0 dac h dac g dac f dac e dac d dac c dac b dac a command bits (c3 to c0) address bits (a3 to a0) dont cares dont cares power- down mode power-down/power-up channel selectionset bit to 1 to select resistor network v out resistor string dac 05302-058 power-down circuitry amplifier figure 77. output stage during power-down table 15. clear code register clear code register db1 db0 cr1 cr0 clears to code 0 0 0x0000 0 1 0x8000
ad5629r/ad5669r preliminary technical data rev. pra | page 30 of 33 1 0 0xffff 1 1 no operation table 16. 32-bit input shift register contents for clear code function lsb db23 db22 db21 db20 db19 db18 db17 db16 db15 to db2 db1 db0 0 1 0 1 x x x x x cr1 cr0 command bits (c3 to c0) address bits (a3 to a0 )dont cares dont cares clear code register ldac function the outputs of all dacs can be updated simultaneously using the hardware ldac pin. synchronous ldac : after new data is read, the dac registers are updated on. ldac can be permanently low or pulsed as in figure. asynchronous ldac : the outputs are not updated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the contents of the input register. alternatively, the outputs of all dacs can be updated simulta- neously using the software ldac function by writing to input register n and updating all dac registers. command 0011 is reserved for this software ldac function. an ldac register gives the user extra flexibility and control over the hardware ldac pin. this register allows the user to select which combination of channels to simultaneously update when the hardware ldac pin is executed. setting the ldac bit register to 0 for a dac channel means that this channels update is controlled by the ldac pin. if this bit is set to 1, this channel updates synchronously; that is, the dac register is updated after new data is read, regardless of the state of the ldac pin. it effectively sees the ldac pin as being tied low. (see table 17 for the ldac register mode of operation.) this flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. writing to the dac using command 0110 loads the 8-bit ldac register (db7 to db0). the default for each channel is 0, that is, the ldac pin works normally. setting the bits to 1 means the dac channel is updated regardless of the state of the ldac pin. see table 18 for the contents of the input shift register during the load ldac register mode of operation. power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5629r/ ad5669r should have separate analog and digital sections. if the ad5629r/ad5669r are in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5629r/ad5669r. the power supply to the ad5629r/ad5669r should be bypassed with 10 f and 0.1 f capacitors. the capacitors should physically be as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and low effective series inductance (esi), such as is typical of common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board.
ad5629r/ad5669r preliminary technical data rev. pra | page 31 of 33 table 17. ldac register load dac register ldac bits (db7 to db0) ldac pin ldac operation 0 1/0 determined by ldac pin. 1 xdont care dac channels update, overriding the ldac pin. dac channels see ldac as 0. table 18. 32-bit input shift register contents for ldac register function lsb db23 db22 db21 db20 db19 db18 db17 db16 db15 to db8 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 0 x x x x x dac h dac g dac f dac e dac d dac c dac b dac a command bits (c3 to c0) address bits (a3 to a0) dont cares dont cares setting ldac bit to 1 overrides ldac pin
ad5629r/ad5669r preliminary technical data rev. pra | page 32 of 33 outline dimensions 2.70 2.60 sq 2.50 compliant to jedec standards mo-220-wggc. 012909-b 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.45 0.40 0.35 s eating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 figure 78. 16-lead lead frame chip scale package [lfcsp] (cp-16-17) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 79. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters
ad5629r/ad5669r preliminary technical data rev. pra | page 33 of 33 ad5629r ordering guide model temperature range package description package option power-on reset to code accuracy ad5629racpz 1 ?40c to +105c 16-lead lfcsp cp-16-17 zero 2 lsb inl ad5629rbcpz 1 ?40c to +105c 16-lead lfcsp cp-16-17 zero 1 lsb inl ad5629raruz 1 ?40c to +105c 16-lead tssop ru-16 zero 2 lsb inl AD5629RBRUZ 1 ?40c to +105c 16-lead tssop ru-16 zero 1 lsb inl 1 z = pb-free part. ad5669r ordering guide model temperature range package description package option power-on reset to code accuracy ad5669racpz 1 ?40c to +105c 16-lead lfcsp cp-16-17 zero 32 lsb inl ad5669racpz-3 1 ?40c to +105c 16-lead lfcsp cp-16-17 midscale 32 lsb inl ad5669 rbcpz 1 ?40c to +105c 16-lead lfcsp cp-16-17 zero 16 lsb inl ad5669raruz 1 ?40c to +105c 16-lead tssop ru-16 zero 32 lsb inl ad5669raruz-3 1 ?40c to +105c 16-lead tssop ru-16 midscale 32 lsb inl ad5669rbruz 1 ?40c to +105c 16-lead tssop ru-16 zero 16 lsb inl eval-ad5669rebz-ru eval-ad5669rebz-cp lfcsp evaluation board tssop evaluation board 1 z = pb-free part. ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr08819-0-1/10(pra)

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